IR/EM Analysis & SignOff using Ansys Redhawk, Redhawk-SC & Cadence Voltus

  • PG Grid Planning and Design
  • IR and EM Methodology Development
  • Block and Full-Chip IR Analysis (Static/Dynamic Vector and Vectorless, Dynamic Scan Mode)
  • Block and Full-Chip EM Analysis (Power and Signal)
  • Ramp-Up Analysis

ESD Analysis

  • SoC/Block level Sign-Off at cell level
  • IP ESD Sign-Off till transistor level using industry standard tools
  • Resistance Validation, Current Density Checks, Placement and Connectivity Checks

RDL Routing and Full-Chip Integration Package

  • Bump Planning/Assignment and RDL Routing
  • RDL Push-Down flow (For accurate Block Level EMIR analysis)
  • Full-Chip Integration
  • PG Grid Planning/Design
  • Physical Verification of PG Grid
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